![]() ![]() This means the program loops back to the start of the block after executing the last line. It is also possible to exclude the sensitivity list from our process, in which case the VHDL code inside the process block will run continuously. We can see then that the sensitivity list has a big effect on the way our process blocks function in VHDL. When a relevant event is detected, the process block resumes executing from the first line of code. If we include a sensitivity list in our process, our VHDL code waits at the end of the block until there is an event on one of the signals in this list. When we write a process block in VHDL, each line of the code is run in sequence until we get to the end of the block. It is important that we have a good understanding of process blocks in order to be an effective VHDL designer. These are connected to the fact that we are describing hardware rather than writing software. However, we need to be careful when using process blocks as there are some features which are unique to VHDL. This concept is likely to be quite familiar as it is the way in which conventional programming languages such as C or Java work. The statements in the process construct execute one after another. The code snippet below shows the general syntax for the VHDL process. This is especially important when we describe sequential circuits as we must describe behavior which occurs in a specific sequence. We use the VHDL process keyword to create blocks of code which are executed sequentially. This will allow you to simulate your solutions and prove that they are working as desired. ![]() However, you should consider reading the blog on basic testbenches in VHDL before tackling these exercises. ![]() However, we often have to write more code in comparison to concurrent statement.Īs with the previous blogs, there are a number of exercises at the end of this post. We can also use process blocks to model combinational logic. Therefore, the VHDL programming language features a construct known as the process block which we can use to model these circuits. We also saw how we can use concurrent statements to model the behavior of these circuits in VHDL.Īs concurrent statements execute in parallel, they are not suitable for the modelling of sequential logic circuits. In the post on VHDL logical operators and signal assignment, we talked about the concept of combinational logic circuits. We will look at some of the fundamental features of the process block, including sensitivity lists, variables and assignment scheduling. We mainly look at the process block which we use to write VHDL code which is executed sequentially. In this post, we look at the some of the techniques we can use to model sequential logic circuits in VHDL. ![]()
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